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EL4501
Data Sheet April 28, 2006 FN7327.2
Video Front End
The EL4501 is a highly-integrated Video Front End (VFE) incorporating all of the key signal conditioning functions for analog video signals. It provides a flexible front-end interface for analog or analog/digital video sub-systems. The VFE contains a high bandwidth DC-restore, an advanced sync separator and a data slicer with an adjustable threshold, configurable output and power-down mode. The VFE performs restoration of the DC level (blanking level) of a video signal and the recovery of all signal timing necessary for synchronization and control. Additionally, data embedded in the active video or VBI regions of the video signal may be extracted using the flexible data slicer incorporated into the VFE. The advanced sync separator exhibits excellent noise immunity by incorporating a digital brick wall filter and signal qualification algorithm. The DC-restored video amplifier is unity gain stable with an unloaded -3dB bandwidth of 100MHz. The input common mode voltage range extends from the negative rail to within 1.5V of the positive rail. When driving a 75 double terminated coaxial cable, the amplifier can drive to within 150mV of either rail. With 200V/s slew rate, the amplifier is well suited for composite and component video applications. The VFE operates from a single 5V supply from -40C to +85C and is available in a reduced footprint 24 Ld QSOP package.
Features
* DC-restore and sync separator * Wideband (100MHz) DC-restore * Advanced sync separator * Programmable data slicer * Single 5V operation * Diff gain/phase = 0.05%/0.03, RL = 10k, AV = 1 * Low power (<75mW) * Pb-free plus anneal available (RoHS compliant)
Applications
* Video capture & editing * Video projectors * Set top boxes * Security video * Embedded data recovery
Pinout
EL4501 (24 LD QSOP) TOP VIEW
VFB 1 VIDEO IN 2 24 VIDEO OUT 23 DS OUT 22 DS REF 21 REF IN 20 REF OUT 19 VS 18 VSD 17 SYNC AMP 16 SLICE MODE 15 BACK PORCH 14 ODD/EVEN 13 VERTICAL
Ordering Information
PART NUMBER EL4501IU EL4501IU-T7 EL4501IU-T13 EL4501IUZ (See Note) EL4501IUZ-T7 (See Note) PART TAPE & MARKING REEL EL4501IU EL4501IU EL4501IU EL4501IUZ EL4501IUZ 7" 13" 7" 13" PACKAGE 24 Ld QSOP 24 Ld QSOP 24 Ld QSOP 24 Ld QSOP (Pb-free) 24 Ld QSOP (Pb-free) 24 Ld QSOP (Pb-free) PKG. DWG. # MDP0040 MDP0040 MDP0040 MDP0040 MDP0040
DS MODE 3 DS ENABLE 4 GND 5 GNDD 6 RFREQ 7 FSEL 8 SYNC IN 9
EL4501IUZ-T13 EL4501IUZ (See Note)
MDP0040
LOS 10 COMPOSITE 11 HORIZONTAL 12
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003-2004, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. Manufactured under License, U.S. Patents 5,486,869; 5,754,250
EL4501
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (VS to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V Pin Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V, VS +0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Continuous Current (VIDEO OUT) . . . . . . . . . . . . . 50mA
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER ISA ISD VS VSD
VS = VSD = 5V, GND = 0V, TA = 25C, Input Video = 1VP-P, RFREQ = 130k DESCRIPTION CONDITIONS No load No load, VIN = 0V MIN 7.5 1.9 4.5 4.5 TYP 10.5 2.3 MAX 13.5 4 5.5 5.5 UNIT mA mA V V
Input Supply Current Digital Supply Current Input Supply Voltage Range Digital Input Supply Voltage Range
VIDEO AMPLIFIER SECTION VOP Positive Output Voltage Swing (VIDEO OUT) RL = 150 to VS/2 (Note 1) RL = 150 to GND RL = 1k to VS/2 VON Negative Output Voltage Swing (VIDEO OUT) RL = 150 to VS/2 (Note 1) RL = 150 to GND RL = 1k to VS/2 +IOUT -IOUT dG dP BW Positive Output Current (VIDEO OUT) Negative Output Current (VIDEO OUT) RL = 10 to VS/2 RL = 10 to VS/2 60 -50 4.65 4.20 4.85 4.70 4.60 4.90 0.15 0.06 0.05 70 -60 0.05 0.03 100 60 8 80 96 0/3.5 to 0.1%, VIN = 0V to 3V 35 115 1.5 RL = no load, VOUT = 0.5V to 3V RL = 150 to GND, VOUT = 0.5V to 3V DC-RESTORE SECTION CMIR VOS TCVOS IB Common Mode Input Range (REF IN) Input Offset Voltage Input Offset Voltage Temperature Coefficient Input Bias Current (REF IN) VCM = 0V to 3.5V -10 DC restored 0/3.5 20 10 0.001 10 V mV V/C A 65 50 0.30 0.25 0.20 V V V V V V mA mA % MHz MHz MHz V/s V ns k pF dB dB
Differential Gain Error (VIDEO OUT) (Note 2) AV = 1, RL = 10k, RF = 0 Differential Phase Error (VIDEO OUT) (Note 2) Bandwidth AV = 1, RL = 10k, RF = 0 -3dB, G = 1, RL = 10k to GND, RF = 0 -3dB, G = 1, RL = 150 to GND, RF = 0
BW1 SR VRL tS RIN CIN AVOL
Bandwidth Slew Rate Ref Level Range Settling Time Input Resistance (VIDEO IN) Input Capacitance (VIDEO IN) Open Loop Voltage Gain
0.1dB, G = 2, RL = 150 to GND 25% to 75%, 3.5VP-P, RL = 150, RF = 0
2
EL4501
Electrical Specifications
PARAMETER VREF IRMAX VS = VSD = 5V, GND = 0V, TA = 25C, Input Video = 1VP-P, RFREQ = 130k (Continued) DESCRIPTION Reference Output Voltage (REF OUT) Available Restore Current (VFB) CONDITIONS IOUT = +2mA to -0.5mA MIN 1.15 TYP 1.3 18.5 MAX 1.4 UNIT V A
DATA SLICER SECTION IIH IIL VIH VIL VOH VOL IOUT IB VOS VHYS tPD tR/F Input High Current (DS MODE & DS ENABLE) VIH = 5V Input Low Current (DS MODE & DS ENABLE) VIL = 0V Input High Voltage (DS MODE & DS ENABLE) Input Low Voltage (DS MODE & DS ENABLE) Output High Voltage (DS OUT) Output Low Voltage (DS OUT) Short Circuit Current (DS OUT) Input Bias Current (DS REF) Input Offset Voltage Hysteresis Propagation Delay Rise/Fall Time 50% to 50% 10% to 90%, RL = 150k, CL = 5pF IOUT = -1mA IOUT = +1mA RL = 10 to 2.5V DS REF = 0V to 5V 8 -10 -20 5 18 1.2 4.75 4.9 0.1 11 0.001 10 +20 0.25 4.5 0.5 6 200 10 350 A nA V V V V mA A mV mV ns ns
SYNC SEPARATOR SECTION ZSOURCE (MAX) Maximimum source impedance driving SYNC IN IIH IIL VIH VIL VOH VOL VTHRSHA VTHRSHF VSI RINSI VRANGE tCD tCDF tBD tBDF tHD tBW tHW tHWF tVW tVDD tVDDF Input High Current (FSEL & SYNC MODE) Input Low Current (FSEL & SYNC MODE) Input High Voltage (FSEL & SYNC MODE) Input Low Voltage (FSEL & SYNC MODE) Output High Voltage Output Low Voltage Adaptive Slice Level Fixed Slice Threshold SYNC IN Reference Voltage SYNC IN Input Impedance Input Dynamic Range COMPOSITE Delay COMPOSITE Delay BACK PORCH Delay BACK PORCH Delay HORIZONTAL Delay BACK PORCH Width HORIZONTAL Width HORIZONTAL Width VERTICAL Width VERTICAL Default Delay VERTICAL Default Delay FSEL = 0, from 50% of sync leading edge FSEL = 1, from 50% of sync leading edge FSEL = 0, from 50% of trailing sync edge FSEL = 1, from 50% of trailing sync edge FSEL = 0/1, from 50% of sync leading edge FSEL = 0/1 FSEL = 0 FSEL = 1 FSEL = 0/1, standard NTSC FSEL = 0 FSEL = 1 0.5 25 150 125 250 365 2.8 1.1 1.2 196 26.5 35 225 170 420 470 3.2 1.3 1.5 198 31.2 31.5 IOH = -1.6mA IOL = +1.6mA SYNC MODE = 0V SLICE MODE = VS 40 80 50 100 1.8 115 2.0 45 280 225 550 585 4.1 1.5 1.8 200 35.9 4.6 0.4 60 120 VIH = 5V VIL = 0V -1 -1 4.5 0.5 1000 1 1 A A V V V V % mV V k VP-P ns ns ns ns ns s s s s s s
3
EL4501
Electrical Specifications
PARAMETER fH VLOSE VLOSD tJIT ASA RSA VRFREQ NOTES: 1. RL is Total Load Resistance due to Feedback Resistor and Load Resistor. 2. AC signal amplitude = 286mVPP, F = 3.58MHz, REF IN is swept from 0.8V to 3.4V, RL is DC coupled. Horiz Scan Rate Analog LOS Enable Threshold Analog LOS Disable Threshold Output Jitter SYNC AMP Gain SYNC AMP Output Impedance RFREQ Reference Voltage RFREQ = 13k to 130k 1.15 Minimum sync amplitude to enable outputs Maximum sync amplitude to disable outputs All sync separator outputs 1.7 VS = VSD = 5V, GND = 0V, TA = 25C, Input Video = 1VP-P, RFREQ = 130k (Continued) DESCRIPTION CONDITIONS MIN 15 120 80 5 2.0 200 1.28 1.4 2.3 V TYP MAX 130 UNIT kHz mV mV ns
Typical Performance Curves
4 NORMALIZED MAGNITUDE (dB) 2 0 -2 -4 -6 100K AV=2 RF=1k AV=5 RF=1k VREF_IN=1.3V RL=150 AV=1 RF=0 PHASE ()
45 0 -45 -90 -135 AV=2 RF=1k AV=5 RF=1k VREF_IN=1.3V RL=150 1M 10M 100M AV=1 RF=0
1M
10M
100M
-180 100K
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. NON-INVERTING FREQUENCY RESPONSE (GAIN)
FIGURE 2. NON-INVERTING FREQUENCY RESPONSE (PHASE)
4 NORMALIZED MAGNITUDE (dB) RL=10k 2 0 RL=150 -2 -4 VREF_IN=1.3V RF=0 AV=1 1M 10M 100M RL=1k NORMALIZED MAGNITUDE (dB)
8 CL=39pF 4 0 CL=0pF -4 -8 VREF_IN=1.3V RF=150 AV=1 1M 10M 100M CL=15pF
-6 100K
-12 100K
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. FREQUENCY RESPONSE FOR VARIOUS RL
FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS CL
4
EL4501 Typical Performance Curves (Continued)
4 RF=2k NORMALIZED GAIN (dB) 2 0 RF=500 -2 -4 NORMALIZED GAIN (dB) RF=1k
4 RL=10k 2 0 RL=75 -2 -4 RL=150
AV=2 RL=150 1M 10M 100M
AV=2 RF=1k 1M 10M 100M
-6 100K
-6 100K
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS RF
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS RL
4 NORMALIZED MAGNITUDE (dB) CL=100pF 2 0 CL=15pF -2 -4 VREF_IN=1.3V RF=1k RL=150 AV=2 1M CL=0pF CL=68pF CL=47pF IMPEDANCE () 10 100
AV=1 RF=0
1
-6 100K
10M
100M
0.1 10K
100K
1M FREQUENCY (Hz)
10M
100M
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 8. CLOSED LOOP OUTPUT IMPEDANCE
90 70 GAIN (dB) 50 30 10 -10 1K GAIN RL=150 GAIN RL=10k PHASE RL=150
0 -45 -90 -135 -180 -270 100M PSRR, CMRR (dB) PHASE ()
10
PHASE RL=10k
-10
-30 CMRR -50 PSRR VS PSRR VSD -70 1K 10K 100K 1M 10M 100M
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 10. PSRR AND CMRR vs FREQUENCY - VIDEO AMP
5
EL4501 Typical Performance Curves (Continued)
10K VOLTAGE NOISE (nV/Hz) DIFFERENTIAL GAIN (%)
0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 0.5 RL=10k 1 1.5 2 VOUT (V) 2.5 3 3.5 RL=150 RF=0 AV=1
1K
100
10 10
100
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 11. VOLTAGE NOISE vs FREQUENCY - VIDEO AMP
FIGURE 12. DIFFERENTIAL GAIN FOR RL TIED TO 0V
0.08 DIFFERENTIAL PHASE () 0.04 0 RL=10k -0.04 RL=150 -0.08 -0.12 0.5 DIFFERENTIAL GAIN (%) RF=0 AV=1
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 0.5 RL=10k RL=150 RF=1k AV=2
1
1.5
2 VOUT (V)
2.5
3
3.5
1
1.5
2 VOUT (V)
2.5
3
3.5
FIGURE 13. DIFFERENTIAL PHASE FOR RL TIED TO 0V
FIGURE 14. DIFFERENTIAL GAIN FOR RL TIED TO 0V
0.15 DIFFERENTIAL PHASE () 0.05 -0.05 -0.15 -0.25 -0.35 0.5 RL=150 ACQUISITION TIME (s) RL=10k
1600 AV=2 RF=1k RL=150 VIN=1V STEP VREF_IN=13.V
1200
800
400
RF=1k AV=2 2 VOUT (V) 2.5 3 3.5
0 1 1.5 0 100 200 300 400 500 HOLD CAPACITANCE (pF)
FIGURE 15. DIFFERENTIAL PHASE FOR RL TIED TO 0V
FIGURE 16. ACQUISITION TIME vs HOLD CAPACITANCE
6
EL4501 Typical Performance Curves (Continued)
25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VREF_IN (V) RESTORE CURRENT (A) OFFSET VOLTAGE (mV)
25 20 15 10 5 0 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
FIGURE 17. DC OFFSET VOLTAGE AT VOUT vs VREF_IN
FIGURE 18. DC-RESTORE CURRENT vs TEMPERATURE
10 IDROOP=CH*(VRAMP/T) 1 HOLD STEP VOLTAGE (mV) DROOP CURRENT (nA)
10
V=Q/CH
1
0.1
0.1
0.01
0.001 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
0.01 1 10 100 1K HOLD CAPACITANCE (pF)
FIGURE 19. DROOP CURRENT vs TEMPERATURE
FIGURE 20. HOLD STEP VOLTAGE vs HOLD CAPACITANCE
100 DR=VRAMP/T DROOP RATE (mV/ms) 10
160 140 LINE RATE (kHz) 120 100 80 60 40 20
1
0.1
0.01 1 10 100 1K HOLD CAPACITANCE (pF)
0 0 20 40 60 80 100 120 140 RFREQ (k)
FIGURE 21. DROOP RATE vs HOLD CAPACITANCE
FIGURE 22. LINE RATE vs RFREQ
7
EL4501 Typical Performance Curves (Continued)
160 140 LINE RATE (kHz) 120 100 80 60 40 20 0 10 RFREQ (k) 100 200 BACK PORCH WIDTH, HORIZONTAL SYNC WIDTH (s)
4 3.5 3 2.5 2 1.5 1 0.5 0 0 20 40 60 80 100 120 140 RFREQ (k) HORIZONTAL (FSEL=0) BACK PORCH HORIZONTAL (FSEL=1)
FIGURE 23. LINE RATE vs RFREQ
FIGURE 24. BACK PORCH AND HORIZONTAL SYNC WIDTH vs RFREQ
600 500 DELAY TIME (ns) 400 300 200 100 0 0 20 40 60 80 100 120 140 RFREQ (k) BACK PORCH (FSEL=1) HORIZONTAL COMPOSITE SYNC DELAY (ns)
44 RFREQ=130k 42 40 38 36 34 -40
BACK PORCH (FSEL=0)
20
0
20
40
60
80
100
TEMPERATURE (C)
FIGURE 25. DELAY TIME vs RFREQ
FIGURE 26. COMPOSITE DELAY vs TEMPERATURE FSEL = 0
244 HORIZONTAL SYNC DELAY (ns) COMPOSITE SYNC DELAY (ns) RFREQ=130k 240 236 232 228 224 -40
500 RFREQ=130k 495 490 485 480 475 470 -40
20
0
20
40
60
80
100
20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 27. COMPOSITE DELAY vs TEMPERATURE FSEL = 1
FIGURE 28. HORIZONTAL DELAY vs TEMPERATURE
8
EL4501 Typical Performance Curves (Continued)
35 RFREQ=130k 34 33 32 31 30 -40 BACK PORCH DELAY (ns) DATA SLICER DELAY (ns)
182 RFREQ=130k 180 178 176 174 172 170 168 -40
20
0
20
40
60
80
100
20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 29. DATA SLICER DELAY vs TEMPERATURE DS MODE = 1
FIGURE 30. BACK PORCH DELAY vs TEMPERATURE FSEL = 0
440 RFREQ=130k BACK PORCH DELAY (ns) 435 430 425 420 415 410 -40 BACK PORCH WIDTH (s)
3.72 RFREQ=130k 3.7 3.68 3.66 3.64 3.62 3.6 3.58 -40
20
0
20
40
60
80
100
20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 31. BACK PORCH DELAY vs TEMPERATURE FSEL = 1
FIGURE 32. BACK PORCH WIDTH vs TEMPERATURE
210 VERTICAL SYNC WIDTH (s) POWER DISSIPATION (W) 200 190 180 170 160 RFREQ=130k 150 -40 20 0 20 40 60 80 100
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 1.2 1 0.8
870mW
QS OP
0.6 0.4 0.2 0 0 25
JA =
11 5
24
C/ W
50
75 85 100
125
150
TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 33. VERTICAL SYNC WIDTH vs TEMPERATURE
FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
9
EL4501 Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) 1.2 1
1.136W
Q 88
0.8 0.6 0.4 0.2 0 0 25
JA =
SO P2
4
C /W
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Timing Diagrams
FIELDS ONE AND THREE (ODD) COMPOSITE SIGNAL
COMPOSITE SYNC OUTPUT
BURST/BACK PORCH OUTPUT
HORIZONTAL SYNC OUTPUT
VERTICAL SYNC OUTPUT
ODD/EVEN OUTPUT
FIELDS TWO AND FOUR (EVEN) COMPOSITE SIGNAL
COMPOSITE SYNC OUTPUT
BURST/BACK PORCH OUTPUT
HORIZONTAL SYNC OUTPUT VERTICAL SYNC OUTPUT
ODD/EVEN OUTPUT
10
EL4501 Timing Diagrams
VIDEO IN
COMPOSITE SYNC OUTPUT
tCD BURST/BACK PORCH OUTPUT
tBD tBW
tHD HORIZONTAL SYNC OUTPUT tHW
VIDEO IN
VERTICAL SYNC OUTPUT tCD+t t<< tCD tCD+2t ODD/EVEN
Standard (NTSC Input) H. Sync Detail
tCD
tBW
11
EL4501 Pin Descriptions
PIN NUMBER 1 PIN NAME VFB PIN TYPE Input PIN DESCRIPTION Connection for gain and feedback resistors, RF and RG EQUIVALENT CIRCUIT
VS
GND CIRCUIT 1
2
VIDEO IN
Input
Input to DC-restore amplifier; input coupling capacitor connects from here to video source
VS
GND CIRCUIT 2
3
DS MODE
Input
Sets the mode of the DS comparator; logic low selects a standard logic output; logic high selects an open drain/collector
VS
GND CIRCUIT 3
4
DS ENABLE
Input
Enables the output of the comparator; a logic high enables the comparator; a logic low three-states it
VS
GND CIRCUIT 4
5 6 7
GND GNDD RFREQ
Input Input Input
Analog ground Digital ground Connection for bias resistor that sets the overall timing
VS
GND CIRCUIT 5
12
EL4501 Pin Descriptions
PIN NUMBER 8 PIN NAME FSEL PIN TYPE Input PIN DESCRIPTION Enable/bypass internal brick wall filter; a logic high is used to enable the filter; a logic low to disable it EQUIVALENT CIRCUIT
VD
GND CIRCUIT 6
9
SYNC IN
Input
Input to the sync separator; connects to the video source via a coupling capacitor or to a color burst input filter
VD
GND CIRCUIT 7
10
LOS
Output
Loss of signal output; goes high if no input video signal is detected
VS
GND CIRCUIT 8
11 12 13 14 15 16 17
COMPOSITE HORIZONTAL VERTICAL ODD/EVEN BACK PORCH SLICE MODE SYNC AMP
Output Output Output Output Output Input Output
Composite sync output Horizontal sync output Vertical sync output Odd/even field indicator output Back porch output
Reference circuit 8 Reference circuit 8 Reference circuit 8 Reference circuit 8 Reference circuit 8
Low = 50% slicing level; high = 70mV fixed slicing level Reference circuit 8 Amplitude of sync tip; can be used to control AGC circuit
VS
GND CIRCUIT 9
18
VSD
Input
Digital power supply; nominally +5V
VSD VS
GND CIRCUIT 10
19
VS
Input
Analog power supply; nominally +5V
Reference circuit 10
13
EL4501 Pin Descriptions
PIN NUMBER 20 PIN NAME REF OUT PIN TYPE Output PIN DESCRIPTION Voltage reference for use as blanking level in low cost system EQUIVALENT CIRCUIT
VS
GND CIRCUIT 11
21
REF IN
Input
DC voltage on this pin sets the DC-restore voltage and output blanking level
VS
GND CIRCUIT 12
22
DS REF
Input
Sets the slicing level or reference level for the comparator
VS
GND CIRCUIT 13
23
DS OUT
Output
Output of the data slicing comparator; the output is either open drain or standard symmetrical logic depending on the DS MODE pin
VS
GND CIRCUIT 14
24
VIDEO OUT
Output
Output of DC-restore amplifier
VS
GND CIRCUIT 15
14
EL4501 Block Diagram
VS VSD DS REF
DS MODE + INPUT VIDEO 0.1F DS OUT DS ENABLE VIDEO IN + VIDEO OUT VFB CHOLD + TRACK/ HOLD SYNC IN 0.1F FSEL SYNC AMP LOS RFREQ SYNC SEPARATOR COMPOSITE HORIZONTAL VERTICAL ODD/EVEN + REF IN REF OUT 1.3V CREF BACK PORCH RF RG
FILTER
GND
SLICE MODE
GNDD
Applications Information
Product Description
The EL4501 is a video front-end sub-system comprised of a video amplifier with DC-restore, an adjustable threshold data slicer, and an advanced sync separator. The prime function of the system is to DC-stabilize and buffer AC-coupled analog video signals and to extract timing reference signals embedded in the video signal. An adjustable threshold data slicer incorporated into the EL4501 may be used to extract data embedded within the active video or VBI regions of a video signal.
accumulates over a single line only, before it is corrected. The peak value of drift is limited by the rate of the control signal (typically video line rate) and the AC coupling time constant. The restore loop is comprised of a 100MHz forward video amplifier, combined with a nulling amplifier and sample and hold circuit. For maximum flexibility the hold capacitor is placed off-chip, allowing the loop response rate to be tailored for specific applications and minimizing hold-step problems. The loop provides a restore current peak of 20A at room temperature. Figure 36 shows the amplifier and S/H connection. During normal operation the internally generated DC-restore control signal is timed to the back porch of the video waveform. Figure 37 shows an NTSC video signal, along with the EL4501 BACK PORCH output. In operation, BACK PORCH activates the S/H switch, completing the nulling feedback loop and driving the video amplifier output towards the reference voltage. At the end of BACK PORCH, the external capacitor holds the correction voltage for the remainder of the video line. In the absence of a valid input signal, the chip generates a repetitive, arbitrary restore control signal at the line rate set by the external resistor RFREQ. Although uncorrelated to the input, the pulse
Theory of Operation
DC-RESTORE LOOP When video signals are distributed, it is common to employ capacitive coupling to prevent DC current flow due to differences in local grounds or signal reference levels. However, the coupling capacitor causes the DC level of the signal post capacitor to be dependent on the video (luminance) content of the waveform. A DC-restore loop is used to correct this behavior by moving a portion of the video waveform to a DC reference level in response to a control signal. When the loop is operating, DC drift 15
EL4501
prevents the amplifier output drifting significantly from the DC-restore reference level. This improves start-up behavior and speeds recovery after a signal drop-out. For ease of use, the EL4501 provides a buffered 1.3V DC level normally connected directly to the restore loop reference input (REF IN). Alternatively, an external voltage between 0V and 3.5V, connected to REF IN, can be used to set the restored level.
0.1F VIN ~1.8V + CH
quantity is called the droop current. This droop current produces a ramp in the hold capacitor voltage, which in turn produces a similar voltage at the video amplifier output. The droop rate at the video amplifier output can be found using the following equation:
V RAMP DroopRate = ----------------------t
VOUT
gM GBWP = --------------2C H
S/H
+ gM
Assuming CH = 100pF, from the Droop Rate vs Hold Capacitance curve, the droop rate is about 0.31mV/ms at the video amplifier output at room temperature. In NTSC applications, there is about 60s between auto-zero periods. Thus, there is (0.31mV/ms) * 60s = 18.6V. It is much less than 0.5IRE (3.5mV). This drift is negligible. Choice of Hold Capacitor The EL4501 allows the user to choose the hold capacitor as low as 1pF and it is still stable. A smaller hold capacitor has a faster acquisition time and faster auto-zero loop response, but would increase the droop and hold step error. Also, if the acquisition time is too fast, it would probably give an image with clamp streaking and low frequency noise with noisy signals. Increasing the hold capacitor would increase the acquisition time, lower the auto-zero loop response, lower the droop and hold step error. See the performance curves for the trade-off. Normally, in video (NTSC and PAL) applications, a smooth acquisition might takes about 10 to 20 scan lines. For a hold capacitor equal to 270pF, the acquisition time is about 10 lines. In the worse case, ambient temperature is 85C, the droop current is 2.2nA which causes the output voltage ramp to about 0.49mV for 60s. This drift is negligible in most applications. Figure 38 shows the input and output waveforms of the video amplifier while the S/H is in sample mode. Applying a 1V step to the video amplifier input, the output of the video amplifier jumps to 2.3V. Then, the auto-zero system tries to drive the video output to the reference voltage, which is 1.3V. The acquisition time takes about 10 NTSC scan lines.
CH=270pF
VREF_IN
FIGURE 36. DC-RESTORE AMPLIFIER AND S/H CONFIGURATION
INPUT VIDEO SIGNAL BACK PORCH OUTPUT CH1=500mV/DIV CH3=5V/DIV M=10s
FIGURE 37. NTSC VIDEO SIGNAL WITH BACK PORCH OUTPUT
Auto-Zero Loop Bandwidth The gain bandwidth product (GBWP) of the auto-zero loop is determined by the size of the hold capacitor and the transconductance (gM1) of the sample and hold amplifier. GBWP = gM1/(2 * CH), gM1 is about 1/(29k), for CH = 270pF, GBWP is 20kHz. For CH = 100pF, GBWP is about 55kHz. Charge Injection and Hold Step Error Charge injection refers to the charge transferred to the hold capacitor when switching to the hold mode. The charge should ideally be 0, but due to stray capacitive coupling and other effects, it is typically 6fC. This charge changes the hold capacitor voltage by V = Q/CH and will shift the output voltage of the video amplifier by V. However, this shift is small and can be negligible for the EL4501 (see the Hold Step Voltage Error vs Hold Capacitance curve). Assuming CH = 100pF, V is about 60V. There will be 60V change at the video amplifier output.
VIDEO AMP OUTPUT VIDEO AMP INPUT
CH1=500mV/DIV CH2=1V/DIV M=100s Auto-zero mechanism restores amplifier output to 1.3V after +1V step at input
FIGURE 38. INPUT AND OUTPUT WAVEFORMS WITH S/H IN SAMPLE MODE
Droop Rate
When the S/H amplifier is in the hold mode, there is a small current that leaks from the switch to the hold capacitor. This 16
EL4501
DATA SLICER The data slicer is a fast comparator with the output of the video amplifier connected to its inverting input and the DS REF connected to its non-inverting input. The DS OUT is logical inverse of the video output sliced at the DS REF voltage. The propagation delay from the video amplifier output to the DS OUT is about 18ns. There is about 10mV hysteresis added internally in the comparator to prevent the oscillation at the DS OUT when the voltages at the two inputs are very close or equal. An adjustable DS REF voltage may be used to extract data embedded within the active video or video blanking interval regions of a video signal. Logic low at the DS ENABLE pin enables the comparator and logic low lets the DS OUT be three-state. The DS MODE pin sets the mode of the DS comparator. Logic low at the DS MODE pin selects a standard logic output and a logic high selects an open drain/collector output. VIDEO AMPLIFIER The EL4501 DC-restore block incorporates a wide bandwidth, single supply, low power, rail-to-rail output, voltage feedback operational amplifier. The amplifier is internally compensated for closed loop feedback gains of +1 or greater. Larger gains are acceptable but bandwidth will be reduced according to the familiar Gain-Bandwidth product. Connected in a voltage follower mode and driving a high impedance load, the amplifier has a -3dB bandwidth of 100MHz. Driving a 150 load, the -3dB bandwidth reduces to 60MHz while maintaining a 200V/s slew rate. CHOICE OF FEEDBACK RESISTOR, RF The video amplifier is optimized for applications that require a gain of +1. Hence, no feedback resistor is required. However, for gains greater than +1, the feedback resistor forms a pole with the hold capacitance. As this pole becomes larger, phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few picofarad range in parallel with RF can help to reduce ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, RF + RG appear in parallel with RL for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently RF also has a minimum value that should not be exceeded for optimum performance. * For AV = +1, RF = 0 is optimum * For AV = +2, RF between 300 and 1k is optimum VIDEO PERFORMANCE For good video signal integrity, an amplifier is required to maintain the same output impedance and frequency response as DC levels are changed at the output. This can be difficult when driving a standard video load of 150 because of the change in output current with DC level. A look at the Differential Gain and Differential Phase curves will help to obtain optimal performance. Curves are provided for AV = +1 and +2, and RL = 150 and 10k. As with all video amplifiers, there is a common mode sweet spot for optimum differential gain/differential phase. For example, with AV = +1 and RL = 150 and the video level kept between 1V and 3V, the amplifier will provide dG/dP performance of 0.17%/0.07. This condition is representative of using the amplifier as a buffer driving a DC coupled, double terminated, 75 coaxial cable. Driving high impedance loads, such as signals on computer video cards gives much better dG/dP performance. For AV = 1, RL = 10k, and the video level kept between 1V and 3V, the dG/dP are 0.03%/0.02. SHORT-CIRCUIT CURRENT LIMIT The EL4501 video amplifier has no internal short circuit protection circuitry. Short circuit current of 90mA sourcing and 65mA sinking typically will flow if the output is shorted midway between the rails. If the output is shorted indefinitely, the power dissipated could easily increase the die temperature such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds 50mA. This limit is set by internal metal interconnect limitations. Obviously, short circuit conditions must not be allowed to persist or internal metal connections will be damaged or destroyed. DRIVING CABLES AND CAPACITIVE LOADS The EL4501 video amplifier can drive 39pF loads in parallel with 150 with 5dB of peaking. For less peaking in theses applications a small series resistor of between 5 and 50 can be placed in series with the output. However, this will obviously reduce the gain slightly. If your gain is greater than 1, the gain resistor RG can be adjusted to make up for any lost gain caused by the additional output resistor. Peaking may also be reducing by adding a "snubber" circuit at the output. A snubber is a resistor in series with a capacitor, 150 and 100pF being typical values. The advantage of a snubber is that it does not draw DC load current. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, the back-termination series resistor decouples the video amplifier from the cable and enables extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can reduce peaking. VIDEO SYNC SEPARATOR The EL4501 includes an advanced sync separator, which is used to generate the DC-restore control signal and seven major sync outputs. The advanced sync separator operates at a 5V DC (pin VSD) single-supply voltage. The input signal source is composite video with levels of 0.5VP-P to 2.0VP-P.
17
EL4501
Low jitter, temperature-stable timing signals are generated using a master time-base, embedded within the system. Line rate is adjustable from 10kHz to 135kHz using a single external resistor (RFREQ). An integrated, pin-selectable digital filter tracks line rate and rejects high frequency noise and video artifacts, such as color burst. In addition to the digital filter, a window-based, time qualification scheme is employed to improve recovered signal quality. During loss of signal, all outputs are blanked to prevent output chatter caused by input noise. The maximum total source impedance driving the SYNC IN pin should be 1k or lower. Source impedances greater than 1k may reduce the ability of the EL4501 to reliably recover the sync signal. Composite Sync Output The composite sync output is a reproduction of the signal waveform below the composite video black level, with the video completely removed. The composite video signal is AC-coupled to SYNC IN (pin 9). The video signal passes through a comparator whose threshold is controlled by the SLICE MODE pin. The output of the comparator is buffered to the COMPOSITE output (pin 11) as a CMOS logic signal. Horizontal Sync Output The horizontal circuit triggers on the falling edge of the sync tip of the input composite video signal and produces a horizontal output with pulse widths about 12 times the internal oscillator clock. For NTSC video input, the pulse width of the horizontal sync is 1.5s, with the digital filter selected. The half line pulses present in the input signal during vertical blanking are removed with an internal 2H-eliminator circuit. Vertical Sync Output A low-going vertical sync pulse is generated during the start of the vertical cycle of the incoming composite video signal. The vertical output pulse is started on the first serration pulse in the vertical interval and is ended on the second rising edge during the vertical serration phase. In the absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 31s after the last falling edge of the vertical pre-equalizing pulse for RFREQ = 130k. Back Porch Output In a composite video signal, the chroma burst is located on the back porch of the horizontal blanking period and is also the black level reference for the subsequent video scan line. The back porch is triggered from the rising edge of the sync tip. The pulse width of the back porch is about 29 times the internal oscillator clock cycle. For the NTSC video input, the pulse width of the back porch is about 3.5s. In EL4501, the back porch pulse controls the sample and hold switch of the DC-restored loop.
CH2=2V/DIV M=2ns
Odd and Even Output For a composite video signal that is interlaced, there is an odd field that includes all the odd lines, and an even field that consists of the even lines. The odd and even circuit tracks the relationship of the horizontal pulses to the leading edge of the vertical output and will switch on every field at the start of vertical sync pulse interval. ODD/EVEN, pin 14 is high during the odd field and low during the even field. Sync Amplitude Output The output voltage at the SYNC AMP output (pin 17) is about 2 times the sync tip voltage. This signal can be used for AGC applications. When there is no sync signal at the input, the SYNC AMP output is 0V. Loss of Sync Output Loss of video signal can be detected by monitoring the LOS output at pin 10. LOS goes low indicating the EL4501 has locked to the right line rate. LOS goes high indicating the EL4501 is out of lock. When there is loss of sync, all the sync outputs go high, except ODD/EVEN. Digital Filter Operation The EL4501 contains a user-selectable digital filter which tracks the line rate and rejects high frequency noise and video artifacts, such as color burst. Basically, the digital filter delays all signals and filters out the pulses which are shorter than the filters delay time. The digital filter greatly reduces the jitters in the outputs. With the digital filter on, the jitter at the composite sync output is only 2ns. Figure 39 shows the jitter at the output when the digital filter is selected. However, the output waveforms will be delayed from 150ns to 300ns due to this filter. Refer to the performance curves for details. Applying logic high to the FSEL pin, the digital filter is enabled. Applying a logic low to the FSEL pin, the digital filter is disabled.
FIGURE 39. JITTER AT THE OUTPUTS WITH FSEL=1
RFREQ An external RFREQ resistor, connected from pin 7 to ground, produces a reference current that is used internally as the timing reference for all the sync output delay time and output pulse widths. Decreasing the value of RFREQ increases the reference current and frequency of the internal oscillator,
18
EL4501
which in turn decreases the reference time and pulse width. A higher frequency video input requires a lower RFREQ value. The Line Rates vs RFREQ performance curve shows the variation of line rate with RFREQ. Slice Mode and Operation with VCRs Normally the signal source for the EL4501 is assumed to be clean and relatively noise free. If that is the case, the SLICE MODE pin (pin 16) should be connected to ground, which sets the slice level to 50% of the sync tip. Some signal sources may have excessive video peaking, causing high frequency video and chroma components to extend below the black level reference, such as VCR signals which generate lots of head switching noise. In this case, the SLICE MODE pin should be connected to logic high which sets the slice level to a fixed 100mV above the sync tip. Also, a single pole chroma filter is required at the composite video input to increase the S/N ratio of the incoming noisy video signal. When the source impedance is low, typically 75, a 620 resistor in series with the source and 470pF capacitor to ground will form a low pass filter with a roll-off frequency of about 550kHz. This bandwidth sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal and high frequency spikes, yet passes the sync pulse portion without appreciable attenuation. The chroma filter will increase the propagation delay from the composite sync input to the outputs. Applying a chroma filter, setting the SLICE MODE pin and FSEL pin to high greatly improve the noise immunity performance in VCR applications. Output Drive Capability The outputs of the sync separator are not designed to drive heavy loads. For a 5V VDS, if the output is driving 5k load to ground, the output high voltage is about 4.9V. If the output is driving 500 load, the output high voltage is down to 4.2V. where: * TJMAX = Maximum junction temperature (125C) * TAMAX = Maximum ambient temperature (85C) * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the product of total quiescent supply current and power supply voltage, plus the power in the IC due to the load. Assume no load at the sync separator outputs:
V OUT P DMAX = V S x I SMAX + V SD x I SDMAX + ( V S - V OUT ) x --------------RL
The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
where: * VS = Supply voltage * VSD = Digital supply * ISMAX = Maximum supply current * ISDMAX = Maximum digital supply current * VOUT = Maximum output voltage * RL = Load resistance tied to ground
Board Layout
As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. In normal operation, where the GND pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS to GND will suffice. To reduce cross talk between the analog signal path and the embedded sync separator, a separate digital supply pin, VSD is included on the EL4501. This pin should be bypassed in a similar manner to VS. For additional isolation a ferrite bead may be added in line with the supply connections to both pins. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance.
General
Power Dissipation
With the high output drive capability of the EL4501 video amplifier, it is possible to exceed the 125C Absolute Maximum junction temperature under certain load current conditions. It is important to calculate the maximum junction temperature for a given application to determine if load conditions or package type need to be modified for the amplifier to remain in its safe operating region.
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